OpenSparc-T2 Synthesis-Part 4 (Block Level Impl till GDSII)

This is final and last part of the Open Sparc T2 processor synthesis series. Actually, I wont be posting anything new here, but just for completeness sake of the series, I’m creating a new post.  Sorry about this, but I dont see any point in reposting the same thing twice.

The P&R script for block level implementation can be picked from my earlier post Nova H.264 decoder core P&R script

 

The flow starts from post fix time script. You need to import the fix cell final volcano after the SMC are implemented using fix cell $m $l -prototype in part-3 and start from there.

I have to admit that you might need to tweak the P&R script  to get good QOR since processor cores are higher frequencies and timing closure approach will be  different. But the script is a good start and can easily take to 60-70% mark .

For folks who are reading this directly, there are 4 parts for OpenSparcT2 processor core and the order is as follows

1. Part 1: This post deals with bottom-up synthesis of all major blocks in OpenSparcT2

2. Part-2 : This is top level synthesis & integration of all the synthesized sub blocks in part 1

3. part-3 : This is to build the floorplan for the full processor core by partitioning/shaping, pin assignment, block level timing budgets. After Part-3 is done, the blocks are ready for full P&R implementation.

4. Part4 : This is final part and allows you to complete the block level P&R implementation all the way to GDSII

For the records, I have used Opteron m/c with Linux and used Magma Design Automation’s Implementation tools (Talus Platform – Talus Design & Talus Vortex ) along with the best of the breed hierarchical floorplan tool Hydra.

Thanks for reading!! Hope this 4 part series helps you to synthesize and implement the full opensparc-T2 processor . Have fun!!!

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Synthesis and Implementaion (P&R) of low-power realtime H.264/AVC baseline decoder

As the title says, anyone interested in Video decoder of H.264 can check the Verilog code from Open Cores. Many kudos to the author for giving the detailed spec .  There are few cores which has decent feature set
and this is one of  them. For details and features , please visit the OpenCores/Authors webpage at :

http://www.opencores.org/projects.cgi/web/nova/overview

Apart from reusing the valuable cores as IP, open cores is also a valuable resource for someone willing to learn different aspects of the design from RTL-GDSII .

Design Stats & snapshots

Full Chip Layout

Full Chip Layout - Nova

Clock-Tree

Nova-CTS

Congestion

nova-congestion

Pin and Cell Density

Nova- Cell DensityNova- Pin Density

Technology Node: 45nm process
Clock Freq: 333 MHz (Please note, I have changed the clk freq. I was scaling the clk freq to see study design feasibility . However , it might be possible to close timing by bumping the freq higher, I havent done that as this is intended purely for fun and learning purposes )


  • Used non default rules with double spacing during CTS
  • We also enable cross talk and cross talk noise based optimizations during detailed routing.

Std Cell Area:0.744mm2 with 70% util and 3.8 mts wire length
Cell Count : 176K
Scan Insertion : Done. No of scan chains 6

EDA Tools: Talus Design for Logic Synthesis,
Talus Vortex for Placement,Clock Tree Synthesis and Routing
Power:  ( We havent really done too many power optimizations except Clock gating which helps on dynamic power) .  I will try to post another version of script where I did many power optimizations to save leakage/dynamic power while not hurting timing. The cell count/area and wire length are direct consequence of tightening the clock freq.

Another reason why over constraining is bad :) . as long as the tool is predictable and have very good front end – back end correlation, you dont need to over constraint. Synthesis tools like Talus Design and from other vendors offer correlation in range 6-10%  range or may be less in some cases ( please note this largely depends on design/timing criticality/whether macro intensicve etc).

Based on spec, I have written some timing constraints to take the design through the entire flow.  I havent got time to close timing, but it was nearly close. The final timing is about -50ps and is easily fixable with few signal DRC left ( less than 30 ) .

The full flow script/timing cons/relevant script are pasted below.
############
import volcano  library.volcano
set m /work/nova/nova
set l /library

config rtl clockgate on -integrated $l/ICG
config rtl verilog 2000 on
config map clockedge on
config rtl datapath physical off
config primary unique off
config timing clockgating on
config timing inout net on
config timing inout cell off
config timing slew default generation on
config sdc unit capacitance p
config sdc unit resistance k
config sdc unit time n
config timing clock multiple on
config timing borrow method relax
config timing borrow automatic on
config timing slew mode largest
config timing propagate constants combinational
config timing check recovery on
config volcano -crash.volcano off
config snap error_volcano off
config async concur off
config snap output on [config snap level] volcano prefixtime-dft-insert-scan
config message limit SWP-8 1
config message limit MAP-111 1

config multithread -thread auto -feature all -gr on

set rtl_list [glob ../src/*.v ]
eval import rtl -verilog -include ../src $rtl_list

fix rtl $m

config snap replace [config snap level] fix-netlist-sweep ” run gate sweep $m -hier -cross_boundary -uniquify ”
run bind logical -no_uniquify $m $l

force dft scan style $m muxed_flip_flop
force gate opt_mode $m delay -hier
fix netlist $m $l -effort high
export verilog netlist $m snap/compile_mingate.v -minsize

# Scan Insertion starts here
enwrap “config dft scan lockup on
config dft scan shift_register on
config dft setup clock_groups on
config dft repair violation clock_violation on
config dft repair violation comb_loop on
config dft repair violation disable_tribus on
config dft repair violation latch on
config dft repair violation reset_violation on

” prefixtime-dft-configure $m

enwrap {
force dft scan clock $m [list $m/mpin:clk]

for {set sid 0} {$sid < 6 } {incr sid} {
data create port [data only model_entity $m] SI${sid} -direction in
data create port [data only model_entity $m] SO${sid} -direction out
force dft scan chain $m $sid SI${sid} SO${sid}
}

force dft scan control $m $m/mpin:SE scan_enable

} prefixtime-dft-force $m

enwrap “run dft check $m -pre_scan
run dft scan insert $m
run dft check $m -post_scan
run dft scan trace $m ” prefixtime-dft-insert-scan $m

# Scan Insertion Ends here

# Source Timing Constraints
source -echo $SCRPATH/nova_constraints.tcl

enwrap {
force undriven $m 0
run gate sweep $m -hier -cross_boundary
} pre-ftime-sweep $m

#To enable pipeliing with 5 stages and using clk as clock and also to enable retiming , uncomment below 2 lines
#force gate pipeline $m $l -stage 5 -clk $m/clk
#force gate retime $m on -hier

# Turn on netlist level clock gating. Helps saves area by eliminating feedback
# loops with muxes and helps in routing due to lesser number of pins

config gate clockgate on

# Use sized netlist flow and use new mapper with -smap option
set  FT_FLOW sized
fix time $m $l -effort high -timing_effort high -size -smap

enwrap {
export verilog netlist $m snap/logic_opt_mingate.v
} ftime-export-verilog $m

enwrap {
config hierarchy separator “_”
data flatten $m
} flatten-design $m

### Floorplanning  starts here

enwrap {
force model routing layer $m highest M6

force plan net VDD $m -usage power -port VDD
force plan net VSS $m -usage ground -port VSS

config optimize leakage on -auto on
config capacitance congestion true

} floorplan-configs $m

set fp [ data create floorplan $m fp ]
run floorplan size $fp -target_total_util 0.5 -aspect_ratio 1.0
config autoflow $m set fix_plan
config autoflow $m set fix_shape

fix power $m $l -default_mesh -auto_domains -mesh_range { M4 M5 }

enwrap { run plan create pin $m -incremental } pin-pl-incr $m

config flow $m set floorplan
check design $m

if {[data exists /macro_lib ] } {
export volcano ./snap/floorplan.volcano -object /work -object /macro_lib } else {
export volcano  ./snap/floorplan.volcano -object /work }

#Floorplanning ends here

#Spare Cell Insertion
config snap procedure spare_flops {
global SCRPATH
#Spare Cells to be created are defined in sparE_cell.tcl and they are attached to VSS net and belong the floorplan of $m
run plan create sparecell $m $SCRPATH)/spare_cell.tcl VSS -floorplan [data only model_floorplan $m ]
run plan identify sparecell $m -file snap/spare_cells_identified.tcl
run plan place sparecell $m
puts “nn Executing spare flops proc nn” }

config snap output on [config snap level] spare_flops -snap after fix-cell-place-global1

#force boundary_cell $m -cell “*BND_UF*” -blockage buffer

#Sub Cap and End Cap Insertion
enwrap {
run plan create subcaps $m -subcap [ find_model FILL $l ] -stepdistance 120u
set welltie [find_model FILL $l ]
run plan create endcaps $m -left_endcap $welltie -right_endcap $welltie
} cap-insertion $m

# While Scan reordering, dont order the first flop
config scan optimize $m -not_order_first_flop on

fix cell $m $l -timing

fix opt global $m $l -effort high -label 1

enwrap {
config clock auto_skew_balance on
force plan clock $m -buffer $l/BUF/BUF_HYPER
force plan clock $m -inverter $l/INV/INV_HYPER
force plan clock $m -max_skew 50ps -max_useful_skew 40ps
force timing adjust_latency $m boundary_average } PRE-FIXCLOCK $m
config snap replace  [ config snap level ] fix-clock-route-clock “run route clock $m $l -nondefaul
t_mode double_s -shielding_mode noleaf -effort high -overdrive 3
fix clock $m $l -weight skew -critical_slack 0ps -clock_effort high -timing -nondefault_mode double_s -shielding_mode noleaf

fix opt global $m $l -effort high -dont_move_reg -critical_slack 0ps -secondary_effort off -label 2

fix hold $m $l

enwrap {
config prepare access mode enhanced -ui on
run prepare model access $m -reset
run prepare model access $m
config route flow adaptive $l on
} pre-fix-wire-eap-wrapper $m

fix wire $m $l -slew -crosstalk_delay -crosstalk_effort high

enwrap { config condition case both } rod-case-both $m

enwrap { run place detail $m -eco } rod-rpd-eco $m

run optimize detail $m $l -dont_move_reg -critical_slack 10ps -optimize all -hold_fix_hold_margin 10p -hold_fix_setup_margin 100p -useful_skew

# DRC Cleanup
enwrap {
check route drc $m
check route spacing_short $m
run route refine $m
run route final -incremental -reroute_tile_width 30 $m
run route final -incremental -reroute_tile_width 60 $m
run route final -incremental -reroute_tile_width 20 $m
run route final -incremental -reroute_tile_width 10 $m
run route final -incremental -reroute_tile_width 30 -effort maximum $m
run route final -incremental -reroute_tile_width 60 -effort maximum $m
run route final -incremental -reroute_tile_width 10 -effort maximum $m
run route final -incremental -reroute_tile_width 30 -effort maximum $m
run route final -incremental -reroute_tile_width 50 -effort maximum $m
run route refine $m -type nontrivial
run route refine $m -type notch
run route refine $m -type island
check route antenna $m
check route drc $m
} post-fix-wire-opt-wrapper $m

###########

####Timing Constraints #######

force timing clock {mpin:clk} 3ns -waveform { -rise 0p -fall 1.5ns} -context /work/nova/nova

###############################################################################
# Collect all inputs with some exclusions
###############################################################################
set Inputs [data list “model_pin -direction in” $m]
set Bidirs [data list “model_pin -direction inout” $m ]

# Add the inout ports to the list of inputs

set Inputs [concat $Inputs [data list “model_pin -direction inout” $m ]]

# Remove the clock ports from the list of constrainable inputs

foreach clockPort [data list model_clock $m ] {
set Inputs  [lsearch -all -inline -not -exact $Inputs $clockPort]
}

puts “The number of inputs is     : [llength $Inputs]”

set io_delay_max [ expr [ expr 1.0 / 1500000.0 ] * 0.9 ]
set io_delay_min [ expr [ expr 1.0 / 1500000.0 ] * 0.1 ]

foreach iport $Inputs {
puts “Adding input delay on port $iport”
force timing delay clk $iport -time {-worst  6e-07p  } -type rising_edge  -context $m
force timing delay clk $iport -time {-best 6.66666666667e-08p } -type rising_edge  -context $m
}

###############################################################################
# Collect all outputs with some exclusions
###############################################################################

set Outputs [data list “model_pin -direction out” $m]
set Bidirs [data list “model_pin -direction inout” $m ]
# Add the inout ports to the list of outputs
set Outputs [concat $Outputs $Bidirs]
puts “The number of outputs is    : [llength $Outputs]”

foreach oport $Outputs {
puts “Adding output delay timing check to output port $oport”
force timing check $oport clk -time  6e-07p -type setup_rising  -context $m
force timing check $oport clk -time  6.666666667e-08p -type hold_rising   -context $m
}
###############################################################################
# Assign a default input transition time or set a driving cell if you rather.
###############################################################################
foreach iport $Inputs {
puts “Setting input transition on port $iport”
force timing slew  $iport { -rise {-max 0318p} }
force timing slew  $iport { -rise {-min 0008p} }
force timing slew  $iport { -fall {-max 0314p} }
force timing slew  $iport { -fall {-min 0004p} }
}

###############################################################################
# Assign default loads
###############################################################################
foreach oport $Outputs {
puts “Setting load on port $oport”
force load capacitance $oport {-worst 0.181p }
force load capacitance $oport {-best  0.001p }
}

##########################################################################
puts “Multicycle the async applied inputs”
##########################################################################
set a01  [data list “model_pin -direction in” $m -names {.*mpin:reset_n}]

catch {set a01 [concat $a01] }
foreach p $a01 {
puts “Adding MCP through scan control input $p”
force timing multicycle -from $p -cycles 7 -type setup -reference start
force timing multicycle -from $p -cycles 6 -type hold  -reference start
}

##########################################################################
puts “Set timing constants”
##########################################################################
# Define functional mode
force timing constant $m/mpin:SE 0

return
##########################################################################
puts “Multicycle the output ports that are async in nature”
##########################################################################
set a01 [data list “model_pin -direction out” -names .*mpin:ready.* $m]
set a02 [data list “model_pin -direction out” -names .*mpin:erfound.* $m]
catch {set a01 [concat $a01 $a02] }
foreach aport $a01 {
puts “Setting MCP to async input port $aport”
force timing multicycle -to $a01 -cycles 5 -type setup -reference start
force timing multicycle -to $a01 -cycles 4 -type hold  -reference start
}

##########################################################################
puts “Set max delay on IO through path, use rarely”
# Mindelay and Maxdelay should be the last resort.
##########################################################################
set a01  [data list “model_pin -direction in” $m -names {.*mpin:some_goofy_input}]
set b01  [data list “model_pin -direction out” $m -names {.*mpin:some_goofy_output}]
foreach p $a01 {
puts “Adding min/max delay through input $p”
force timing maxdelay 1.0n -from $a01 -to $b01
force timing mindelay 0.5n -from $a01 -to $b01
}

#####Spare Cells Addition  (spare_cells.tcl) ######

spare_and2 $l/AND2/AND4 20
spare_inv  $l/INV/INVD3 20
spare_buf  $l/BUF/BUF2P 20
spare_nand $l/NAND2/ND4P 20
spare_or $l/OR2/OR4P 20
spare_nor $l/NOR4/NRD2P 20
spare_ff  $l/SDFF/SDFF2 20

###########

OpenSparc-T2 Synthesis -Part 3 ( Hierarchical Floorplan Creation/Refining )

This is continuation of Posts 1 and 2 which adress the block level synthesis and top level synthesis of the opensparct2 processor . This post concentrates on building the floorplan/SDC etc suitable for block level P&R implementation. Due to short of time and bandwidth, I couldnt get a chance to build the floorplan for full chip “cpu” module, but to keep the momentum going and for enthusiasts, I built the flow for the “rtx” module which is quite big ( around 7M+ instances ) below and can act as good testcase to build the reference flow. Anyone who has the full cpu fix-time-final volcano from your top level synthesis run, can load it in place rtx or alternatively import the full chip netlist and follow the rest of the flow.

Folks can re-use the P&R implementation script for block level  from my Nova Processor Core RTL-GDSII post .

We are using channel style and the script below basically does the following :

 

1. Floorplan creation
2. Domain creation
3. Partitions the design based on the configs
4. Shapes the floorplan
5. Pin Assignment based on Global Routes
6. Power Ring/Mesh/pin tapping/via creation
7. Buffer long wires
8. Hierarchical top level CTS
9. Block level budget creation
10. Block level P&R implementation of the partitions created above

Exploration using Blackboxes is also covered.

A disclaimer first :) . As I mentioned in my previous post , Please note that, these scripts are not meant to use for any commerical purposes and strictly for personal/learning purposes only and provided “as-is” . Neither the scripts I provided below nor the work is endorsed and has nothing to do with my employer . Additionally please make sure you read all the disclaimers/license agreements when you download the cores.

Couple of Snapshots for this design:

After design is partitioned. RTX block is assumed to be top level here..After design is partitioned. RTX block is assumed to be top level here..
After design is partitioned..RTX block is assumed top levelAfter design is partitioned..RTX block is assumed top level
After Hierarchical CTS is done..RTX is againAfter Hierarchical CTS is done..RTX is again assumed top here

assumed top here

Congestion report among the channels and in top levelCongestion report among the channels and in top level
Auto Partition report Auto Partition report
Channel Report which shows desired sizes of the channel

Now the  script :

#############################################
### Template Script
#######################################################################################

### Design Import & Parameters ###

set design rtx
set m /work/${design}/${design}
set l /std_cell_lib
#If you are reading netlist, change this to 1 and set the netlist dir
set netlist 0
set netlist_dir ./blk-level-synthesis

if { ![data exists $l ] } {
import volcano  45nm_7m_std_cell_library.volcano
}

if { $netlist == “0″ && [data exists $m ] == “0″ } {
import volcano rtx%fix-time-final.volcano
} else {
import netlist $netlist_dir/rtx%fix-time-final%verilog.v

}

config multithread -thread auto -feature timer
config multithread -thread auto -feature delay
config multithread -thread auto -feature optimization
config multithread -thread auto -feature route -gr on
config prepare hyper on
force delay adaptive_buffering $m on -hierarchical on

clear readonly $l
run prepare hyper $l

config volcano -crash.volcano off
config snap error_volcano off
config message level TA-280 warning
### For snap volcano, only output work lib to save disk space
config snap procedure “volcano” {
if { [data exists /macro_lib ] } {
export volcano $outputPrefix.volcano.tar.gz -object /work -object /macro_lib
} else  {
export volcano $outputPrefix.volcano.tar.gz  -object /work
}
}

config snap output on [config snap level ] volcano rhy-*
config snap output on [config snap level ] volcano fix-clock-proto-final
config snap output on [config snap level ] volcano fix-clock-hier-final
config snap output on [config snap level ] volcano fix-budget-setup-buffer-final
config snap output on [config snap level ] volcano fix-budget-buffer-final
config snap output on [config snap level ] volcano fix-budget-final

set all_libs [data list root_lib / ]
set all_libs [lsearch -all -inline -not $all_libs /work ]
set all_libs [lsearch -all -inline -not $all_libs /macro_lib ]
eval “run bind logical $m $all_libs ”

enwrap {
source -echo $data_dir/clear_clk_magma.tcl

force undriven $m 0

if { [regexp fix-time-final [query snap history $m ] ] } {
message info OPST-1 “Fix time is already done..so skipping this step n”
} else {

foreach tmp [data list model_cell $m ]  {
if { [regexp “/work/” [data list cell_model $tmp ] ] } {
lappend ckeep [data only cell_model $tmp ]
force keep [data only cell_model $tmp ] -content
message info OPST-1 “force keep applied on sub block [data only cell_model $tmp ]”
}
}

config snap replace [config snap level ] fix-time-run-gate-clockgate “”
config snap replace [config snap level] fix-time-speed-* “run gate speed $m $l -effort low”
config snap replace [config snap level] fix-time-rof* “”
config snap replace [config snap level ] fix-time-optimize-strength-speed  “run optimize strength $m $l -prototype ”
run timing adjust endpoint $m -external
run gate sweep $m -hier -cross_boundary

fix time $m $l -effort low -timing_effort low

foreach tmp $ckeep {
clear keep $tmp -content
message info OPST-2 “clear kept sub block $tmp”
}
set bufferl [data list model_cell_leaf -attr {repeater_reason 6} $m]
puts “destroy_all_assign_buffers: Unkeeping buffers, entities”
data loop c model_cell_leaf -attr {repeater_reason 6} $m {
clear keep $c
clear keep [data only cell_model $c]
}

puts “destroy_all_assign_buffers: Removing [llength $bufferl] buffers”
run gate unbuffer $m $l -cell $bufferl
set bufferl [data list model_cell_leaf -attr {repeater_reason 6} $m]
puts “destroy_all_assign_buffers: [llength $bufferl] buffers remain”

} rhy-initial-setup $m

#Set this variable to 1 , if you have stubs as opposed to full netlist.
set bbox 0
set scan 0

if { $bbox == “1″} {
### Specify Blackbox Floorplan Parameters (OPTIONAL) ###
report blackbox cells $m
run plan uninitialize blackbox $m/<sub_blks>
rule model /work/sub_blk/sub_blk -type no_type
report blackbox cells $m
force blackbox parameters /work/sub_blk/sub_blk -width 1150u -height 375.9u
run plan initialize blackbox $m -replace
force location cell “$m/sub_blk” floating ;# temporary, to enable move
run plan move cell “$m/sub_blk” { 307.175u 297.765u  } EAST
force location cell “$m/sub_blk” fixed
report blackbox cells $m

}
### Perform Scan Tracing (OPTIONAL) ###

enwrap {
if { $scan == “1″} {
config scan optimize $m -hierarchy on
run dft scan trace $m
}
} rhy-scan-trace $m

### Create Power Domains (OPTIONAL) ###
enwrap {
force library rail $l VDD12
force library rail $l VSS
set pgn VSS
data loop ent lib_entity $l {
data loop port entity_port $ent {
if {[data get $port name]==$pgn} {
message info OPST-1 “Assigning rail $pgn to port $port of $ent.”
rule port use $port ground -rail VSS
}
}
}

set pgn VDD12
data loop ent lib_entity $l {
data loop port entity_port $ent {
if {[data get $port name]==$pgn} {
message info OPST-1 “Assigning rail $pgn to port $port of $ent”
rule port use $port power -rail VDD12
}
}
}

data create domain $m default
set dom1 [ data list model_domain $m ]
force domain primary /work/$design/$design/domain:default
force domain process /work/$design/$design/domain:default 1.000000 -case best
force domain process /work/$design/$design/domain:default 1.000000 -case worst
force domain temperature /work/$design/$design/domain:default -40.000000 -case best
force domain temperature /work/$design/$design/domain:default 125.000000 -case worst
force domain net /work/$design/$design/domain:default VSS ground -primary -supply_type constant
force domain voltage /work/$design/$design/domain:default VSS 0.000000 -case best
force domain voltage /work/$design/$design/domain:default VSS 0.000000 -case worst
force domain rail /work/$design/$design/domain:default VSS /std_cell_lib VSS
force domain net /work/$design/$design/domain:default VDD12 power -primary -supply_type constant
force domain voltage /work/$design/$design/domain:default VDD12 1.260000 -case best
force domain voltage /work/$design/$design/domain:default VDD12 1.080000 -case worst
force domain rail /work/$design/$design/domain:default VDD12 /std_cell_lib VDD12
force derate method user -domain /work/$design/$design/domain:default

data loop fp model_floorplan $m {
data attach $fp floorplan_domain $dom1
}
run domain apply $m -create_mpins
clear readonly $l
run prepare hyper $l -domain $dom1

} rhy-domain $m

# Tie cell connection (OPTIONAL)
# run gate tiecell with local_tie_off

### Create Initial Top-Level Floorplan ###
enwrap {
data create floorplan $m $design
data attach $m/floorplan:$design floorplan_domain $dom1
#force floorplan parameters $m/floorplan:$design -width 2350u -height 2350u -left_margin 250u -right_margin 250u -top_margin 250u -bottom_margin 250u
run floorplan size $m/floorplan:$design -target_total_util 0.6 -aspect_ratio 1
#The above command will create the following parameters
#force floorplan parameters {/work/$design/$design/floorplan:$design} -width 0.01376346 -height 0.01376346 -left_margin 445u -right_margin 445u -bottom_margin 450u -top_margin 375u
run floorplan apply $m -allow_wayward -bucket_size 2_cellrow
} rhy-fp $m

enwrap {
### Create Pad Ring ###
run plan create padring $m -automatic cell_name
} rhy-pad $m

### Place Macros & Logic Clusters ###

enwrap {
run plan create pin $m
run place cluster $m -timing_effort medium -macro_style overlapping -effort low

} rhy-icp-1 $m

### Auto Partitioning
enwrap {

config partition allow_clock_output on
config partition effort high
config partition floorplans_outside off
config partition max_cell_count 350000
config partition min_cell_count 90000
config partition optimize pin_count on
config partition optimize size_balance on
#Before below place corr config is set, make sure design is placed using initial cluster pl otherwise it will issue fatal error
config partition optimize placement_corr on

run plan partition auto $m

## Check whether the partitioning is complete or not?
check plan partition $m -complete

report plan partition candidates $m
} rhy-auto-partition $m

enwrap {

# Commit hierarchy
run plan hierarchy commit $m -no_overlay
} rhy-hier-commit $m

### Specify Design-Wide Shaping Parameters (OPTIONAL) ###
enwrap {
force shape parameters $m -boundary_width 200u -channel_width 50u
query plan shape $m

# force plan blockage parameters $m -enable all -automatic on
# force plan halo -top 15u -bottom 15u -left 5u -right 5u $m $macro_cell
# force plan clearance $m -left 10u -bottom 5u -right 10u -top 5u $macro_cell

### Perform Floorplan Shaping ###
config prepare hyper on
force delay adaptive_buffering $m on -hierarchical on
run place cluster $m -shape -macro_style optimized -timing_effort medium

} rhy-shape $m

enwrap {
set no_of_mlayers [query layer routing $m ]
set higher_mlayer [lindex $no_of_mlayers [expr [llength $no_of_mlayers] -3 ] ]
set lower_mlayer [lindex $no_of_mlayers [expr [llength $no_of_mlayers] -4 ] ]
set m1_layer [lindex $no_of_mlayers 0 ]
#ring
force route power2 ring $m  top -ring {VSS {METAL6 12u 1.5u horizontal} {METAL5 12u 1.5u vertical}} -ring {VDD12 {METAL6 12u 16.5u horizontal} {METAL6 12u 16.5u vertical}}

run route power2 ring $m  -style separate -inner_shape -specs {top}

#mesh
force model routing layer $m highest $higher_mlayer
force route power2 mesh $m v7 -orientation vertical -wire ” VDD12 METAL6 4.0u 0.6u -extend both ” -wire ” VSS METAL6 4.0u 5.8u -extend both ”

run route power2 mesh $m -specs {v7} -inner_shape -group_spacing 30u -macro_clip_range 10u

force route power2 mesh $m h6 -orientation horizontal -wire ” VDD12 METAL5 4.0u 0.6u -extend both ” -wire ” VSS METAL5 4.0u 5.8u -extend both ”

run route power2 mesh $m -specs {h6} -inner_shape -group_spacing 30u -macro_clip_range 10u
#vias and rail
run route power2 rail $m -macro_clip_range 10u -extend_left -extend_right
force route power2 via $m mesh2rail -from {METAL1 rail} -to {METAL6 mesh} -stack {{VIA12 1 1} {VIA23 1 1} {VIA34 1 1} {VIA45 1 1} {VIA56
1 1}}
run route power2 via $m -specs_only -specs mesh2rail
run route power2 pin $m -start_bend 10u -tap_all_pin_layers -pin_type pg

# Connect signal pins that are driven by constant cells to the supply nets
run domain apply $m
run gate constant2power $m

} rhy-power $m

enwrap {
config flow $m set placement

if { $scan == “1″ } {
config scan optimize $m -hierarchy on
run scan optimize $m $l
}
### Buffer High Fanout Nets ###
run gate buffer wire $m $l -balance_hfn -min_hfn_size 30 -skip_lwb
run place clean $m
} rhy-rgbw1-rpc1 $m

enwrap {

### Configure the Global Router for coarse-grain level buckets, 1×1 buckets (OPTIONAL) ###

config route global channel_style $m -preference macro -minimize_channel_vias on
run route global $m -hierarchy -bw -largenet  -override_sign_in_check

} rhy-grx1 $m

enwrap {
config message level PO-100 info
config message level PO-113 info
run plan pushdown transit $m -mode pushdown_areas_only

run pin assign $m -pin_mode global

config route global channel_style $m -preference channel -minimize_channel_vias on
run route global $m -hierarchy -bw -override_sign_in_check

} rhy-grx3-nrpb $m

enwrap {
run plan partition commit $m
run prepare macro timing $m boundary
config limit optimize -type fanout strict
run gate buffer wire $m $l -balance_hfn -global -acc
run route global $m -point_pin -hierarchy -bw -override_sign_in_check

run optimize strength $m $l -iteration 3
run prepare macro timing $m full
run place clean $m

} rhy-grx4-commit $m

### Perform Clock Tree Synthesis (OPTIONAL) ###
config place detail -tolerate_hyper_cells

fix clock_hier $m $l

enwrap {
data pushdown power $m -boundary_cross always

} rhy-pushdown-power $m

### Push Down Scan Infrastructure (OPTIONAL) ###
#data loop x model_soft_macro $m {
#   report dft scan push_down $m -block $x -file [data get $x name].scan.rpt
#   }

### Push Down Blockages (OPTIONAL) ###
# data pushdown physical $m -placement_blockages

fix budget $m $l -setup_buffer

### Perform SMC Prototype Placement (OPTIONAL) ###
config check design type undriven_pins -severity warning
config check design type outside_corebox_wires -severity warning
config check design type undriven_nets -severity warning
config check design type wire_offgrid -severity warning

data loop cell model_soft_macro $m {
set model [data only cell_model $cell]
set bbox [query cell is_blackbox $cell]
if { $bbox == 0} {
puts “running fix cell on $model”
config route global channel_style $model -preference macro
fix cell $model $l -prototype -override_sign_in_check
} else {
puts “skipping fix cell on $model because it is a black box”
}
}

### Perform Top-level Prototype Placement (OPTIONAL) ###
config check design type shrunk_bbox_model -severity info
fix cell $m $l -prototype

### Hand-off to Talus Vortex for Block Implementation ###
# force model view
# export view

return

OpenSparc-T2 Synthesis -Part 2 ( Top level Synthesis )

OK as promised earlier, here are the part2 top level synthesis -cpu module I’m assuming that the block level synthesis using bottom-up flow is done using part-1 and all Glassboxes (Magma’s Terminology for abstracts which are BTW efficient that ILM’s etc and are very suitable for implementing multi-million instances designs) are generated.
There is not much to describe, but essentially the concept is to import & elaborate the top level rtl and
then import the block level GlassBoxes, do the area optimization on top level, perform timing analysis/optimization
by importing sdc (for top level glue logic if any ) and then generate the full top level netlist.

At the end of flow, the front end designers have a choice of either to create  top level netlist with empty stubs (just module definitions with port interface) or full hierarchical netlist . Typically if you have access to bigger m/c around 128G of ram and quad-core or >8 CPU, can bear run times then you can go ahead with full hierarchical netlist

Folks can also take advantage of run prepare timing which creates a basic timing checks like clock,IO delay constraints . You can add more if you want to, but this should be enough to do basic timing analysis.

To do all of this, Ofcourse, you need access to magma’s binaries with appropriate licenses ( Talus Design for Front End, Talus Vortex for P&R implementation and Hydra for Building better floorplans faster )

Now the fun part is to synthesize. Before I post the script, a disclaimer first :) . As I mentioned in my previous post , Please note that, these scripts are not meant to use for any commerical purposes and strictly for personal/learning purposes only and provided “as-is” . Neither the scripts I provided below nor the work is endorsed and has nothing to do with my employer . Additionally please make sure you read all the disclaimers/license agreements when you download the cores.

Stay tuned for my next post (Part-3 ) which will contain scripts to do the hierarchical floorplan ( Build the floorplan ) .

OK now the scripts :

set DV_ROOT /projects/sparc/OpenSPARCT2

set rtl_files [ glob $DV_ROOT/*/*/*.v ]
set include_paths {
-include $DV_ROOT/sys/iop/dmu/rtl
-include $DV_ROOT/sys/iop/pcie_common/rtl
-include $DV_ROOT/sys/iop/niu/rtl
}

config message level VER-61 off
config message level VLOG-457 off
config message level VLOG-90 off
config message level VLOG-188 warning
config message level BND-18 warning
config message limit VLOG-457 1
config message limit VLOG-90 1
config message limit VLOG-101 1
config message level RTL-90 warning
config message level RTL-2027 off
config message level VLOG-102 warning
config message level VLOG-7 warning
config rtl verilog 2000 on
#config rtl LRM_version IEEE_1800_2005

set SCRPATH /projects/sparc/OpenSPARCT2/scripts
set l /std_cell_lib
set design cpu
#set design ccu
set m /work/$design/$design

if { ![data exists $l ] } {
import volcano  45nm_7m_std_cell_library.volcano
}

set spare 0
set enforce_input_fanout_one     0
set allow_outport_drive_innodes  1
set add_lockup_latch 1
config rtl verilog 2000 on
config map clockedge on
config rtl datapath physical off
config timing inout cell off
config timing threshold slew 25 55 45 75
config timing clockgating on
config timing inout net on
config timing slew default generation on
config sdc unit capacitance p
config sdc unit resistance k
config sdc unit time n
config timing clock multiple on
config timing borrow method relax
config timing borrow automatic on
config timing slew mode largest
config timing propagate constants combinational
config timing check recovery on
config rtl clockgate on -integrated $l/CKLHQD16BWP
config view directory  block_views
config volcano -crash.volcano off
config snap error_volcano off

### For snap volcano, only output work lib to save disk space
config snap procedure “volcano” {
if { [data exists /macro_lib ] } {
export volcano $outputPrefix.volcano -object /work -object /macro_lib
} else  {
export volcano $outputPrefix.volcano -object /work
}
}

config message limit LC-21 1
config message level CK-23 warning
config message level CK-347 warning
config message level TA-280 warning
config message level RTL-2027 info
config message level LC-73 info
config message level LAVA-976 info
config message level CK-41 info
config message level NAM-4 info
config message level CZ-10 info
config message level WIRE-9 info
config message level OPTO-171 info
config message level OPTO-169 info
config message level CK-26 info
config message level SWP-8 info
config message level BLKB-102 off
config message level RTL-71 warning
config timing derate cell 1.2 -case worst -late -type data
config message limit SWP-8 1
config message limit MAP-111 1
config message level CND-102 off

config dft scan shift_register on
config gate clockgate off
config primary unique off
#config timing flatten buffer $l/BUF_2/BUF_2_HYPER
config optimize fanout -fanout_limit 16

config snap procedure post-fix-netlist {
### report high-fanout nets
config report clone {PROBLEM CAUSE SINK SLACK MODEL_NAME PIN_NAME NET_NAME}
report clone $m -problem -trace -number 100 -file snap/clone.rpt
}

config snap output on [config snap level] post-fix-netlist fix-netlist-final

## Config timing report
config snap procedure fix-time-rpt {
config report timing detail {PIN_NAME PIN_DIR SINK AT RT SLACK EDGE CLOCK_FLAG PRIMARY_PHASE PHASE}
config report timing path {PIN_NAME:50 MODEL_NAME DELAY SLEW AT SLACK ADAPTIVE_BUFFERS PIN_LOAD WIRE_LOAD SINK}
}

config snap output on [config snap level] fix-time-rpt fix-time-start

#Fix Cell Snap Procedures
config snap procedure mcpu {
config multithread -thread auto -feature route -gr on
config multithread -thread auto -feature all
}

config snap procedure hier_uniquify {
global m
foreach tmp [ data list model_cell $m ] {
if { [data list cell_model $tmp ] == “” } {
data uniquify $m -cell $tmp
} else {
data uniquify $m -entity [data list model_entity [data list cell_model $tmp ] ]

}
}
}

if { ![data exists $m ] } {
eval import rtl -verilog -analyze $include_paths $rtl_files

}
if { $spare == 1 } {
eval run rtl elaborate $design -spare register -arithmetic auto

config report rtl registers -latches off -clock off -tri off -output off -fileinfo off -range off -sync off -async off -range off -header off -summary off -details on -usermodel_only on
data loop le lib_entity /work {
data loop em entity_model $le {
set spare_reg  [ report rtl registers $em -string -noheader  ]
foreach sp $spare_reg {
if { [data exists $em/$sp ] && [regexp  “cell” [data get $em/$sp type] ]} {
if {[query rule model $em -type] eq “standard”} {
force rtl spare_register on $em/$sp
force keep $em/$sp
message info OST-1 “Applied spare_reg attr on $em/$sp and preserved the spare register”
}
}
}
}
}

} else {
eval run rtl elaborate $design  -arithmetic auto

}

fix rtl $m

foreach v $blk_with_views_final {
import volcano [query view directory ]/work/$v/$v/fixtime.volcano -merge
force keep /work/$v/$v -content
}

run prepare blackbox stub $m
run bind logical -no_uniquify $m $l /work

fix netlist $m $l -effort high -scan
force maintain $m -hier

fix time $m $l -timing_effort high -effort high -slack 0ps  -size

################################################################################
##### Delete the glass boxes
################################################################################
export volcano $snapdir/${design}%fix_time_glass.volcano
foreach v $blk_with_views_final {
data delete object /work/$v/$v
}

################################################################################
##### Import the full designs
################################################################################
import volcano ./fullViews/or1200_cpu_full.volcano      -merge
import volcano ./fullViews/or1200_dmmu_top_full.volcano -merge
import volcano ./fullViews/or1200_immu_top_full.volcano -merge

foreach v $blk_with_views_final {
import volcano ./fullViews/$v_full.volcano -merge
}
run bind logical $m $l
run bind logical $m /work
check design $m -file $snapdir/${design}_postFixtime_check_design.rpt
# Use enwrap to dump reports and volcanoes
enwrap {} undo-glassbox $m

enwrap {
config hierarchy separator “_”
data flatten $m
} flatten-design-postftime $m

############################################
# Scan Insertion for full chip
#Optionally one can use the Scan insertion script below at block level/bottom-up synthesis and do top level scan insertion while doing top level #integration.
############################################
enwrap {

if { [info exists add_lockup_latch ] && ($add_lockup_latch == 1) } {
config dft scan lockup on
}
config dft scan shift_register on
config dft setup clock_groups on
config dft scan chain_mix clock on
config dft repair violation clock_violation on
config dft repair violation comb_loop on
config dft repair violation disable_tribus on
config dft repair violation latch on
config dft repair violation reset_violation on

force dft scan clock $m [list $m/mpin:$clk_name]
force dft scan control $m $m/mpin:$scanenable_port scan_enable
for {set sid 0} {$sid < $chain_count } {incr sid} {
data create port [data only model_entity $m] SI${sid} -direction in
data create port [data only model_entity $m] SO${sid} -direction out
force dft scan chain $m $sid SI${sid} SO${sid}
}
} scan_setup $m

enwrap {
run dft check $m -pre_scan
} pre-scan-check $m
enwrap {
run dft scan insert $m
} scan-insertion $m
enwrap {
run dft check $m -post_scan
} post-scan-check $m
enwrap {
run dft scan trace $m
} scan-trace $m

enwrap {
data flatten $m -rtl_inferred_models
export volcano snap/${design}_full.volcano -object $m

set m1 $m
set modelName  [lindex [split $m1 /] 3]
force model view $m1 fixtime
export view $m1  -force
run prepare glassbox abstract $m1 -modeling timing

puts “Bottom up synthesis done for $design ”
} gen-gb-views-ftime $m

return

OpenSparc-T2 Synthesis -Part 1

For anyone interested in learning processor architectures and synthesizing processor cores, they can refer to www.opensparc.net . Sun Micro has donated its entire sparc processor core to Opensource.  They even provide scripts for Synthesis using Synopsys DC and for Verification as well.

Due to my previous back ground and interest in Processor Architectures, given my current CAD background, I was very curious to learn and synthesize these cores. Also, the synthesis scripts are for to use with TALUS platform from Magma. The scripts will do the bottom-up synthesis & top level synthesis, Scan Insertion, Timing Optimization and will write a sized netlist .

Please note that, these scripts are not meant to use for any commerical purposes and strictly for personal/learning purposes only and provided “as-is” . Neither the scripts I provided below nor the work is endorsed and has nothing to do with my employer . Additionally please make sure you read all the disclaimers/license agreements when you download the cores.

Due to short of bandwidth and resources in mind, I’m only publishing logic synthesis scripts. May be time permitting, I will publish the P&R scripts in Part 2 series.

OpenSparc-T2 has the following features and this runs at 1.4GHz (714ps clock period )
8 Sparc cores, 8 threads each
Shared 4MB L2, 8-banks, 16-way associative
Two 10/1 Gb Enet ports w/onboard packet classification and filtering
One PCI-E x8 1.0 port

OpenSparc T2 LayoutOpenSparc T2 Layout . Courtesy opensparc.net

Main modules in the design are :
CCX – Crossbar
CCU – Clock control
DMU/PEU – PCI Express
EFU – Efuse (redundancy)
ESR – Ethernet SERDES
FSR – FBDIMM SERDES
L2B – L2 write-back buffers
L2D – L2 Data  L2D – L2 Data
L2T – L2 tags
MCU – Memory controller
MIO – Miscellaneous I/O
PSR – PCI-Express SERDES
RDP/TDS/RTX/MAC – Ethernet
SII/SIO – I/O datapath in/out to memory
SPC – Sparc core
TCU – Test control unit

PCI-E is not provided with the binary when you download and its a seperate IP.
cpu  is the top level module name .

The following source browser might help everyone when navigating through the hierarchy and for understanding RTL .

 

Scripts:
set DV_ROOT /projects/sparc/OpenSPARCT2

set rtl_files [ glob $DV_ROOT/*/*/*.v ]
set include_paths {
-include $DV_ROOT/sys/iop/dmu/rtl
-include $DV_ROOT/sys/iop/pcie_common/rtl
-include $DV_ROOT/sys/iop/niu/rtl
}

config message level VER-61 off
config message level VLOG-457 off
config message level VLOG-90 off
config message level VLOG-188 warning
config message level BND-18 warning
config message limit VLOG-457 1
config message limit VLOG-90 1
config message limit VLOG-101 1
config message level RTL-90 warning
config message level RTL-2027 off
config message level VLOG-102 warning
config message level VLOG-7 warning
config rtl verilog 2000 on
#config rtl LRM_version IEEE_1800_2005
set SCRPATH scripts
set l /std_cell_lib
#set design cpu
#set design ccu
#set m /work/$design/$design

if { ![data exists $l ] } {
import volcano  45nm_7m_std_cell_library.volcano
source $SCRPATH/patch_lib.tcl
clear readonly $l
}

set spare 0
set enforce_input_fanout_one     0
set allow_outport_drive_innodes  1
set add_lockup_latch 1
config rtl verilog 2000 on
config map clockedge on
config rtl datapath physical off
config timing inout cell off
config timing threshold slew 25 55 45 75
config timing clockgating on
config timing inout net on
config timing slew default generation on
config sdc unit capacitance p
config sdc unit resistance k
config sdc unit time n
config timing clock multiple on
config timing borrow method relax
config timing borrow automatic on
config timing slew mode largest
config timing propagate constants combinational
config timing check recovery on
config rtl clockgate on -integrated $l/CKLHQD16BWP
config view directory  block_views
config volcano -crash.volcano off
config snap error_volcano off

### For snap volcano, only output work lib to save disk space
config snap procedure “volcano” {
if { [data exists /macro_lib ] } {
export volcano $outputPrefix.volcano -object /work -object /macro_lib
} else  {
export volcano $outputPrefix.volcano -object /work
}
}

config message limit LC-21 1
config message level CK-23 warning
config message level CK-347 warning
config message level TA-280 warning
config message level RTL-2027 info
config message level LC-73 info
config message level LAVA-976 info
config message level CK-41 info
config message level NAM-4 info
config message level CZ-10 info
config message level WIRE-9 info
config message level OPTO-171 info
config message level OPTO-169 info
config message level CK-26 info
config message level SWP-8 info
config message level BLKB-102 off
config message level RTL-71 warning
config timing derate cell 1.2 -case worst -late -type data
config message limit SWP-8 1
config message limit MAP-111 1
config message level CND-102 off

config dft scan shift_register on
config gate clockgate off
config primary unique off
#config timing flatten buffer $l/BUF_2/BUF_2_HYPER
config optimize fanout -fanout_limit 16

config snap procedure post-fix-netlist {
### report high-fanout nets
config report clone {PROBLEM CAUSE SINK SLACK MODEL_NAME PIN_NAME NET_NAME}
report clone $m -problem -trace -number 100 -file snap/clone.rpt
}

config snap output on [config snap level] post-fix-netlist fix-netlist-final

## Config timing report
config snap procedure fix-time-rpt {
config report timing detail {PIN_NAME PIN_DIR SINK AT RT SLACK EDGE CLOCK_FLAG PRIMARY_PHASE PHASE}
config report timing path {PIN_NAME:50 MODEL_NAME DELAY SLEW AT SLACK ADAPTIVE_BUFFERS PIN_LOAD WIRE_LOAD SINK}
}

config snap output on [config snap level] fix-time-rpt fix-time-start

#Fix Cell Snap Procedures
config snap procedure mcpu {
config multithread -thread auto -feature route -gr on
config multithread -thread auto -feature all
}

proc luniq {L} {
# removes duplicates without sorting the input list
set t {}
foreach i $L {if {[lsearch -exact $t $i]==-1} {lappend t $i}}
return $t
} ;# RS

proc block_syn {mod} {
global rtl_files rtl_files1  rtl_files2  rtl_files3  rtl_files4  rtl_files5
global DV_ROOT l design m SCRPATH spare
global enforce_input_fanout_one allow_output_drive_innodes add_lockup_latch element

message info SPLC-1 “n Now synthesizing $mod …stay tuned..n”
set default_clk_transition  0.05
set default_hold_skew  0.0
set default_setup_skew  0.0
set default_clk_transition  0.05
set ideal_net_list { cmp_gclk_c2_ccx_left cmp_gclk_c2_ccx_right }
set false_path_list {}
set max_transition   0.15
set max_fanout         6
# default input/output delays
set default_input_delay  0.15
set default_output_delay 0.2
set default_clk gclk
set clk_name_list [list]
set ideal_inputs [list]
set design $mod
set m /work/$mod/$mod
if { ![data exists $m ] } {
eval import rtl -verilog -analyze  $include_paths $rtl_files $rtl_files

if { $spare == 1 } {
eval run rtl elaborate $design -spare register -arithmetic auto

config report rtl registers -latches off -clock off -tri off -output off -fileinfo off -range off -sync off -async off -range off -header off -summary off -details on -usermodel_only on
data loop le lib_entity /work {
data loop em entity_model $le {
set spare_reg  [ report rtl registers $em -string -noheader  ]
foreach sp $spare_reg {
if { [data exists $em/$sp ] && [regexp  “cell” [data get $em/$sp type] ]} {
if {[query rule model $em -type] eq “standard”} {
force rtl spare_register on $em/$sp
force keep $em/$sp
message info OST-1 “Applied spare_reg attr on $em/$sp and preserved the spare register”
}
}
}
}
}

} else {
eval run rtl elaborate $design  -arithmetic auto

}
}

config message level POPT-2 warning
config message level POPT-3 warning
config multithread -thread auto -feature all

fix rtl $m

enwrap {
if { [data exists /work/clock_multiplier_10x ] } {
data delete object /work/clock_multiplier_10x
run gate sweep $m -hier
}
} remove-clock-mult-${design} $m

config async concur off
set all_libs [data list root_lib / ]
set all_libs [lsearch -all -inline -not $all_libs /work ]
set all_libs [lsearch -all -inline -not $all_libs /macro_lib ]
set all_work_libs [data find / work* -type lib ]
eval “run bind logical -no_uniquify $m $all_libs ”

enwrap {
run prepare blackbox stub $m
} prepare-stubs $m

run prepare blackbox stub $m

config sweep sequential on -keep_float off -cycle on

force dft scan style $m muxed_flip_flop
config snap replace [config snap level] fix-netlist-sweep ” run gate sweep $m -hier -cross_boundary ”

fix netlist $m $l -effort high -scan

set clk_port_pin [lindex $element 0 ]
set clk_name [lindex $element 0 ]
set clk_freq [lindex $element 1 ]
set setup_skew [lindex $element 2 ]
set hold_skew [lindex $element 3 ]
set clock_transition [lindex $element 4 ]
set clk_is_port 1
set clk_exists [data find $m ${clk_port_pin} -regexp -type mpin]
lappend ideal_inputs $clk_name
set clk_period [expr 1000.0 / $clk_freq / 1.0]
set high_time [expr $clk_period / 2.0]

if { [data get $m name] == “ccx” } {
force timing clock $m/$clk_port_pin ${clk_period}ns -waveform [list -rise 0ns -fall ${high_time}ns ] -name $clk_name
force timing clock $m/cmp_gclk_c2_ccx_right ${clk_period}ns -waveform [list -rise 0ns -fall ${high_time}ns ] -name cmp_gclk_c2_ccx_right
force timing margin setup ${setup_skew}ns -to [data find $m $clk_name -regexp -type mpin]
force timing margin hold ${hold_skew}ns -to [data find $m $clk_name -regexp -type mpin]
force timing slew [data find $m $clk_name -regexp -type mpin] ${clock_transition}ns
force timing margin setup ${setup_skew}ns -to [data find $m cmp_gclk_c2_ccx_right -regexp -type mpin]
force timing margin hold ${hold_skew}ns -to [data find $m cmp_gclk_c2_ccx_right -regexp -type mpin]
force timing slew [data find $m cmp_gclk_c2_ccx_right -regexp -type mpin] ${clock_transition}ns
} elseif { [data get $m name ] == “mcu” } {
set mcu_ck_pin_list ” drl2clk l2clk iol2clk”
foreach ck $mcu_ck_pin_list {
set clk_name $ck
if { $clk_name == “drl2clk” || $clk_name ==  “iol2clk” } {
force timing clock $m/$ck ${clk_period}ns -waveform [list -rise 0ns -fall ${high_time}ns ] -virtual  } else {
force timing clock $m/$ck 700ps -waveform [list -rise 0ns -fall 350ps ] -virtual  }

force timing margin setup ${setup_skew}ns -to [data find $m $clk_name -regexp -type mpin]
force timing margin hold ${hold_skew}ns -to [data find $m $clk_name -regexp -type mpin]
force timing slew [data find $m $clk_name -regexp -type mpin] ${clock_transition}ns
}
} else {
force timing clock $m/$clk_port_pin ${clk_period}ns -waveform [list -rise 0ns -fall ${high_time}ns ] -name $clk_name

force timing margin setup ${setup_skew}ns -to [data find $m $clk_name -regexp -type mpin]
force timing margin hold ${hold_skew}ns -to [data find $m $clk_name -regexp -type mpin]
force timing slew [data find $m $clk_name -regexp -type mpin] ${clock_transition}ns

}
set non_ideal_inputs [list]
set Inputs [data list “model_pin -direction in” $m]
set Inputs [concat $Inputs [data list “model_pin -direction inout” $m ]]

foreach input_object $Inputs {
set input_name [data get $input_object name]
set input_is_ideal [lsearch -exact $ideal_net_list $input_name]
if {$input_is_ideal == -1} {
lappend non_ideal_inputs $input_name
} else {
lappend ideal_inputs $input_name
}
}

foreach iport $non_ideal_inputs {
force timing delay $m/$clk_name $iport -time ${default_input_delay}ns
}

set Outputs [data list “model_pin -direction out” $m ]
foreach oport $Outputs {
force timing check $m/$clk_name $oport -time ${default_output_delay}ns
}

data loop oport “model_pin -direction out” $m {
force timing check $m/$clk_name $oport -time ${default_output_delay}ns
}

if {[info exists false_path_list] && ($false_path_list != {}) } {
foreach fp $false_path_list {
force timing false -through $fp }
}

if {[info exists enforce_input_fanout_one] && ($enforce_input_fanout_one  == 1)} {
foreach fo $non_ideal_inputs {
force limit fanout $fo 1
}
}

enwrap {
set sweep_model “”
force undriven $m 0
run gate sweep $m -hier -cross_boundary
if { [query undriven $m  ] != “” } {
foreach obj [query undriven $m ] {
if { [regexp pin [data get $obj type ] ] } {
lappend sweep_model [data get [data list pin_model $obj ] name ]
} else {
lappend sweep_model [data get [data list net_model $obj ] name ]
}
}
set smod [luniq [lsort $sweep_model ] ]
}
if { [info exists smod ] && $smod != “” } {
foreach mobj $smod {
set sweep_mobj_tmp [ data find /work $mobj -regexp -hier -type model ]
foreach sweep_mobj $sweep_mobj_tmp {
force undriven $sweep_mobj  0
run gate sweep $sweep_mobj
}
}
unset smod
}
} sweep-subblk-${mod} $m

enwrap {
run timing adjust endpoint $m -external
} adjust-endpoints-b4-ftime-${mod} $m

enwrap {
data loop mp “model_pin” $m {
if { [data count pin_net $mp] != 0 } {
run gate buffer pin $m $l $mp }
}

data loop mp “model_pin -direction out” $m {
if { [data count pin_net $mp] != 0 } {
run gate buffer pin $m $l $mp }
}

# set this switch to 0 to make sure output port doesn’t driving internal nodes
if {[info exists allow_outport_drive_innodes] && ($allow_outport_drive_innodes == 0)} {
#set_isolate_ports -type inverter [all_outputs]
force buffer setup $m -inverter only
data loop mp “model_pin -direction out” $m {
if { [data count pin_net $mp] != 0 } {
run gate buffer pin $m $l $mp
}
}
clear buffer setup $m
}

}   buffer-b4-fixtime-${mod} $m

fix time $m $l -effort high -timing_effort high -size

enwrap {
data flatten $m -rtl_inferred_models
export volcano fullViews/${design}_full.volcano -object $m

set m1 $m
set modelName  [lindex [split $m1 /] 3]
force model view $m1 fixtime
export view $m1  -force
run prepare glassbox abstract $m1 -modeling timing

} gb-extract-${mod} $m
lappend blk_with_views_final $mod

if { [data exists /work ] } {
data delete object /work }
if { [data exists /macro_lib ] } {
data delete object /macro_lib
}
}

set blk_list ” ccu ccx dmu db0 db1 efu l2b l2t ncu rst sii sio spc tcu mcu rdp tds mac rtx”

foreach mod $blk_list {
switch $mod {
ccu   {
set element  {gclk    1400.0   0.000   0.000   0.05}
block_syn $mod
}
dmu  {
set element  {gclk    350.0   0.000   0.000   0.05}
block_syn $mod
}
ccx  {
set element {cmp_gclk_c2_ccx_left    1400.0   0.000   0.000   0.05}
block_syn $mod
}
db0  {
set element {gclk    1400.0   0.000   0.000   0.05}
block_syn $mod
}
db1  {
set element { gclk    1400.0   0.000   0.000   0.05}
block_syn $mod
}
efu  {
set element  { gclk         1400.0   0.000   0.000   0.05}
block_syn $mod
}
l2b  {
set element {gclk           1400.0   0.000   0.000   0.05}
block_syn $mod
}
l2t   {
set element { gclk           1400.0   0.000   0.000   0.05}
block_syn $mod
}
ncu  {
set element {gclk           350.0   0.000   0.000   0.05}
block_syn $mod
}
rst {
set element { gclk           350.0   0.000   0.000   0.05}
block_syn $mod
}
sii  {
set element {  gclk           350.0   0.000   0.000   0.05}
block_syn $mod
}
sio {
set element { gclk           350.0   0.000   0.000   0.05}
block_syn $mod
}
spc {
set element { gclk           1400.0   0.000   0.000   0.05}
block_syn $mod
}
tcu  {
set element { gclk           350.0   0.000   0.000   0.05}
block_syn $mod
}
mcu  {
set element {  iol2clk           400.0   0.000   0.000   0.05}
block_syn $mod
}
rdp  {
set element { cmp_gclk_c0_rdp    1500.0   0.000   0.000   0.05}
block_syn $mod
}
tds  {
set element { cmp_gclk_c0_tds   1500.0   0.000   0.000   0.05}
block_syn $mod
}
mac {
set element  {cmp_gclk_c1_mac    1500.0   0.000   0.000   0.05}
block_syn $mod
}

rtx  {
set element { cmp_gclk_c0_rtx    1500.0   0.000   0.000   0.05}
block_syn $mod
}
}
}

message info OST-4 ” Block Level Synthesis is done..n”

return

-Kiran Bulusu, Semiconductors Expert, Technologist