Want to transform healthcare..Engage the patient first

The biggest change or revolution in healthcare will only happen when the patient is engaged. Most of the solutions I see in this area are very passive ..Its basically follows the old saying where you can take a horse to a lake , but cannot make it drink the water..You can only push so much. Yes, all the healthcare education, efforts in increasing awareness are all positive steps.

Unless , I misunderstood, one good part of the healthcare reform which Obama introduced was to give money to the patients to shop for the insurance that satisfied their needs. So, in the US healthcare system, where there are 4 parties involved, Individuals-Hospitals-Insurance-Employers with Insurance policy choices limited/controlled by the employer, now the employer can give the same money to the employee to shop around and select the best insurance plan. This complete changes the patient engagement . They are more proactive , will pay close attention to the costs and more likely they will invest their time in understanding preventive care.

Republished all popular posts back…

Recently my blog has been hacked and the wordpress sql db has been corrupted. For some reason, I had backup of everything else except the critical sql db which has all the posts and many useful comments/responses… I had many articles dating back to 2005…Its a big loss to me..Ofcourse lesson learned 🙂

Luckily, waybackmachine.org has come to my rescue. I was able to retrieve all my posts and republish them with the only caveat being all posts are with today’s date..I did’nt retrieve some of them as I felt its useless as they are not relevant given we are in 2012…

If you have bookmarked any article and I haven’t republished, let me know the article name/blog post and I will do the needful….

Lastly, I haven’t blogged for a while due to personal commitments, but will blog going forward. Also, I will be blogging now on healthcare, Wireless sensors, systems design, energy management .

Cisco Valet router or Fon 2.0N

Cisco Valet router or Fon 2.0N :

by kiran on Aug.02, 2010, under General, Technology

Should I buy “ease of setup” Cisco Valet router or “smart router which can get more things done with ease of setup” aka Fon 2.0N .

I’m not writing a PR for Fon 2.0N nor this is a marketing blog for Fonera. I’m working on home automation on a tighet budget and have been looking at various devices and saw the video from cisco valet routers and after reading through the specifications , I had this question: why buy Cisco Valet routers when you can do the same and get more things done for lesser price . I’m talking about the Fon 2.0N router from Fonera . I’m an happy Fon 2.0N user for over 8 months and the setup is a breeze so it should satisfy the networking newbies as well (defaults works as well ) and can create seperate network for outsiders/guests (meaning no need to share you private wireless SSID/WEP keys). So question is why someone should 150$ for just “ease of setup”.. Fon works on opensource and also downloads torrents, converts 3G to Wifi, is media/print server, can handle youtube/picasa/megaupload/rapidshare . It actually serves large audience including newbies/geeks/students/wireless enthusiasts .

check this link from networkworld newsletter where the author tells that linksys E-series routers from cisco itself does all the above with lesser price tag..Even then, Fon 2.0N should be a better choice.

Looks like Cisco is trying to appeal consumers with “ease of setup” as their pitch…but will they succeed or will this be yet another router from cisco…?

What I have to admit is, I liked the product design and from what I have seen, they seem to have avoided the usage of technical terms including “router” :) and they use wireless hot spots/internet access which helps many users though… Since I haven’t tried the router hands-on and my impression was based on the router specs and videos from cisco, I might be wrong as well. If anyone has hands-on experience , let me know or let me know if I’m missing something

Formal verification of SOC

There was an interesting question that was asked during the interview with Moshar from Broadcom

EE Times: Are you using formal verification, and does it reduce the need for simulation and acceleration?

Moshar: We are using formal verification, but I don’t believe it is reducing the scope of the work we need to do. It will help you make sure that your IP is golden, but formal verification really does not apply at the SoC level. You have to go through all the traffic scenarios you need to cover.


It would have been nice if a detailed answer was given ..From the question posed and reading the answer , it appears as if it is a limitation of Formal Verification. I think if you describe in terms of Formal properties using PSL , it would be still possible to formally verify the traffic between various cores on SOC..

I think it would be interesting to know on how companies operating in ESL space view this. As systemC and C based language design becoming popular and support TLM, it would interesting to see how one can extract information from these abstract models and verify the design intentions.

Personalization of Silicon and need for Design Flow Automation

I was just looking at some of the latest anouncements and the prototypes at the recent CES show and if you look at the trend and the products that consumers are crazy about, and if you want to sum it up..The market is all about how much personalization can the users do in the product. Every consumer wants to see himself/herself in the product..so what does this translate it to for the Semi-Conductor industry folks.. “ Personalization of Silicon “..

Look at the famous Apple IPOD ..Many see it as the symbol of the youth…So the closer the silicon is to the hearts the consumers, the better are the chances for product success…But this personalization all comes with a price…Everyone knows pricing is one key element which determines the reach and sucess of the product .

So, the big question is , how can the IC industry reduce its IC design and packaging (I mean chip packaging and not feature/product packaging ) costs  and yet be profitable? The answer partly comes from the EDA industry. Automation of the design flow. It is the degree of automation and the accuracy of the results which it can deliver over a short span of time . Multi-million transistors ( 10M+ transistors) and SOC’s are becoming common and the TTM is becoming shorter day by day. For example, with-in few days/weeks of the Apple’s IPHONE announcement, LG released a similar competetive product with almost the same functionality as IPHONE. Imagine how fierece the competetion is. Each single day counts.

How can the design teams manage this pressure ? Marketing teams often wants to add new features in the last minute. People involved in the IC Design knows what this translates to. It is not a matter of simple ECO . Sometimes a small feature addition can lead to couple of weeks delay. I know a customer who has to do go through the entire design cycle twice as marketing asked them to add 2 more new features each time and this effected their tape-out schedules by 6 weeks..Not every Semi-conductor company can afford such a delay ( especially folks operating in Consumer Electronics market  segment ).  So , the solution doesnt come by adding few more engineers or simply delaying the product launch.. You need design tools which are smart enough to detect the incremental changes anywhere in the flow and automatically do the appropriate steps in the design flow with no or minimum intervention from designer.

Not many EDA companies are recognizing the importance of the automation and their perception of automation is awefully wrong. I would say in years to come, the company which manages to bring the true “automation” of the design flow to the industry will emerge as the real winner.

If your customer makes money, you make money. It is as simple as that.

BTW, You need engineers to find smarter ways to design and bring “true” personalization of the silicon :)

Logic Synthesis Primer

I have recently seen many folks asking questions like “How to write a synthesis script” or “Whats is in a synthesis environment” . Many freshers right out of the school claim to know about synthesis but in reality doesnt have a clue where to start.

When I refer to Synthesis in this post…I mean Logic Synthesis and I mostly cover only logic synthesis and it doesnt include any STA (Timing analysis). I will cover some points which overlap between logic synthesis and front end timing optimization. I will write a seperate post on Front-end timing optimization and Physical Synthesis (Floorplan , Global Placement and Routing , CTS ).

Synthesis is not just a script you write for a specific tool. It is actually much more than that. I have seen many folks who loosly couple it with a specific tool like Synopsys DC or Magma Blast Create. It is in a sense a methodology which evolves over the time by doing many runs as the block/chip evolves. Before you start synthesis , One has to know

1. What are the area goals? If area is one of the important criteria, then one needs to know what are the area reduction techniques available from the tool . I’m assuming that RTL has conforms to best design practices. Check the number of logic levels and cells used after first iteration. Accordingly decide what your strategy for area reduction should be. One benefit of reducing the area will help to comeup with a relatively smaller floorplan. Ofcourse most EDA folks prefer bigger floorplans sothat their floorplanning or placement tools can easily do the job :) , easily avoid the congestion and cross-talk issues :). But I strongly suggest synthesis folks to have some understanding of physical synthesis.

2. What are the power goals? Some tools have advanced power savings schemes in synthesis itself like Power gating flops/Retention flops. They do this when the RTL designer uses some special pragmas in their RTL code and they capture this when the tools parse the RTL.

3. If clock gating allowed? Are there any modules/blocks for which clock gating has to be disabled? You need to understand why it has to enabled/disabled and should be aware of its impact. You should know if the technology library has the support for ICG (Integrated
clock gating cells) .

4.How much hierarchy has to be kept? Keep in mind that Logical Hierarchy is different from Physical Hierarchy. When you decide to maintan hierarchy, it has to be considered that some optimization algorithms are limited by the module hierarchies/boundaries and so care should be taken as if and how much QOR can be sacrificed.

5. Is flattening allowed ? The answer to this question depends partly on the decision you make on the above question. If yes , is it allowed on entire design ? If not, can you atleast do flattening selectively. Other relevant information you need to know is , if rtl inferred models can be flattened .

6. What is your DFT strategy and methodology. Many might wonder why is it important to consider at Logic Synthesis stage. This is especially important when you plan for DFT during RTL development. Like you might have declared the test/scan ports in RTL and since scan insertion will not be done till synthesis has been done, many optimization algos in the synthesis engine will see them as floating and will blow them away. So, you might need to instruct the tool not to touch them.

7. Resource sharing and Operator Merging : If the these options are available in the synthesis and if you dont have any constraint or reason for not using them, then it is highly recommended to take advantage of these . But care has to be taken as some formal tools either dont have good support for this or dont support them at all .

8. Datapath architecture selection : Some advanced synthesis tool allows you to configure/pre-select the datapath architectures . If timing is critical for a particular block, then you might want to overide the area optimization steps by selecting the fastest architecture available for all the datapath components in that particular block. Do remeber that selecting fastest architecture might blow up area sometimes.

9. Formal Verification : FV (Formal Verification) tools dont do agressive optimizations ( or should I say, it is not a good idea to so :) ) as synthesis tools do. So, it is highly important that you let your FV tool know about the synthesis options when exists & possible. You should try to mimic the synthesis env in your FV environment. Else you can see some false failures.

10. Hard Macros : When macros are used and if some of the inputs/outputs are unused, they might be removed. So if any macros or hard instantiated gates are present , you should set the appropriate commandslike force keep or set_dont_touch .

11. Spare gates/registers : When spare registers are described in the RTL itself, synthesis tools should be instructed to preserve them else they are treated as a part of unreachable registers and might be thrown off during
synthesis (deadcode removal ). Some people use spare registers in the backend and sprinkle them evenly.

12. It is important to analyze the technology library for the cell delays and area. One another important factor most people forget is to consider the effect of EM (electro-migration) and yield . All the bad cells ( which have high delays , or bad for EM or yield, bad area ) should be hidden or disabled from being used by synthesis engine. Forgetting to disable cells bad for EM or yield effects timing closure with cross-talk/SI during backend.

Apart from this, make sure all complex cells like AOI, OAI, Full Adders and Half Adders, XOR etc are available to the synthesis tool. It helps save area and increases drive load capability resulting less buffering.

13. Dont use highest effort levels in synthesis by default ( unless you know what you are doing ). Some optimization algorithms might hurt your design by doing agressive optimizations. Synthesis knobs have to be used with care and by studying what it does to the design.

14. Designware usage: Sometimes, it makes sense to use Designware components in RTL . Make sure the synthesis tool used can detect the Designware components , understand and synthesize them. Some synthesis tool vendors change them to their equivalent models ( for example, Lavaware components from magma ) . If not , you might need to black box them and read in the gate level netlist of those designware components after synthesis is done.

15. Pipe-lining : Almost all synthesis tool support this . So where necessary, the designer or synthesis expert has to know which block/module needs pipe-lining ; how many stages are required and what is the latency at each stage etc.

16. Re-Timing : Sometimes when RTL has those designware or lavaware components , some synthesis tools automatically apply re-timing and some synthesis tools require you to explicilty set the relevant re-timing configs . But keep in mind that re-timing is not supported that well in FV tools.

17. Dontcare optimization : If the RTL contains dont-cares (X) , many synthesis tools allow you to choose whether you want x to be treated as “0″ or “1″. I suggest it would be better if we leave it to the synthesis tool to decide. Most dontcare algorithms select the value of x which will result in smaller ckt area if area optimization is enabled or better ckt with better timing if timing mode is enabled.

18. Clock Edge mapping: Some synthesis tool map to neg edge flops and add a inverter if they see that is has better area savings than pickingup a pos edge flop. Some design methodologies especically back-end teams dont prefer this sometimes. So, you need to set the configs accordingly.

19. If there are any complex cells like Full Adders, Half Adders etc with multiple outputs in your library , then most synthesis tools dont utilize them and so if your want to synthesis tool  to use them , then you have to hand instantiate them in RTL. Remeber these cells will be timed, but will not infered or decomped to simpler cells/logic during optimization phases .
With all these said, I cant stress enough how important it is for RTL coders to follow best practices. There is lot of information out there or one can refer to STARC methodology guide or Design-Reuse methodology manual for information .

Genchi Genbutsu Principle..

Genchi Genbutsu : People who have read books about Toyota’s philosphy or who work in Japanese factroys might have known this term already.. Click the link below for small explanation what it means


In a general sense , it can be applied to any industry. I know a R&D director in a decent  startup who doesnt have a clue what the market wants. He sits in his cubicle and visualizes what the market wants and directs his R&D team. I was like what the crap ??. He is technically  brilliant, but if he doesnt know where there is a gap in the market, what is the use of his technical brilliance ???

” what gets developed in R&D, stays in R&D only ”

Logo and Brand of an EDA company

I was just thinking why cant the Marketing folks in EDA companies have a agreement with the Semiconductor companies that when a chip goes to production , their logo is displayed as well. Something like Designed using Magma Design Automation etc., I cant think of reason why Semiconductor companies wont  allow that. I think it will create much more buzz than a press release. It will also expose the EDA industry and the company to outside world . The role played by the EDA industry right from RTL-GDSII and post silicon debug is very important and cant be downplayed .

For example, when we look at the IPOD and scrolldown to a section (something like about us ), you can typically see that the chip is designed by Portal Player etc. So, if Apple allows Portal Players logo to be on IPOD, why cant they allow  EDA company name to be there. Yes, I understand that it is not as simple as it sounds as many chips deisgned by one company gets integrated into another company’s SOC , but still, it can be done through
mutual/joint agreements.

It helps EDA companies to get the recognition they deserve and also it helps EDA companies to attain a brand similar to what product based companies have.

Being an Field Application Engineer

It is a long post (you are warned !! :)
I have been recently asked by someone as what it takes to be sucessful application engineer . So, I thought why not blog about ..Though much of it is written from EDA industry perspective, it applies for appln engineers in other industries as well. So, here it goes ….
1. Technical expertise : You have to be atleast good if not proficient in the domain..for example, lets say, if you are application engineer for a formal verification product, you need to have expertise in the FV techniques and good understanding as what logic/physical synthesis tools do in terms of optimization. Just mere tool knowledge will not suffice..

2. You should be a like a double edged sword ..You need to be able to understand the hardware design…be it RTL , Scan insertion , P&R or CTS and at the same time , you should be able to understand how the algorithm (tool) behaves (from software perspective..)..If you dont understand both, you will not be able to understand what the HW designer is trying to accomplish and at the same time, you will not be able to find out if the tool is missing any feature or is it a limitation of the technology and finally if it is a bug …one more important reason is , you might need to translate the designers intention into a feature speficiation and direct your R&D.

3. Business Sense : I think this is very important component for an Appln engineer. You need to be in constant touch with the customer and get feedback on the product. You should be able to sense the impact derived from that feedback. Whenever there is a oppurtunity to promote a new product, you should do so immediately and let your marketing/sales team know about it immediately. Just being technical is not enough.
Application engineer without good business sense can negatively impact the company he represents.

4. Pre-Sales : Ability to benchmark against the competitor and convince him about your products technical merits. Depending upon the competetion and product and domain in which you operate, this can be very intensive and grilling. Failure is not an option . A true winning aptitude and to do whatever it takes is absolute must. No compromises.
I’m not exagaretting , but it might involve some sacrifices like working during xmas or thanksgiving :) . Pre-Sales campaigns can very stressful and can burn a person. So, if you cant work under pressurized environment and have strict rules about your work timings, then you might not like this role. Believe me there are some customers who keep  evaluating for very long time or they evaluate now and then re-evaluate after couple of months and there are reasons why they do like this ( first and foremost reason is to check the quality of the tool :) ) . So it is tiresome and it requires willingness to walk that extra mile to win the benchmark is a must.
5. Post-Sales/Deployment : A succesful tech campaign and business(pre-saleS) win is the starting step. The 20/80 rule applies here ( 80% of the business comes from 20% of your customers). So, sucessful deployment of the product across the depth and breadth of the company is key . It will also gives Sales folks a chance to push other products
into the company. Dedicated and fast support is one of the strategies. Providing support for their first tapeout with your company’s product is another key. A sucessfull deployment also means to work with the design methodology groups,designers ( front end and backend ), understanding their design goals and issues ; resolving their issues . It might be necessary to come up a design methodlogy /flow either on a project basis or company wide . A constant interaction with the design team is a must . This also helps the appln engineer to see what is lacking and fill in the gaps either through scripting or getting R&D implement the missing features and enhance the product.

6. Evangelism : Not many folks know about this. Some people mix this with the marketing. This is virually non-existent in EDA/semiconductor industry. Marketing is more about the product , evangelism is creating a community around the product. Who else can be a better person other than the appln engineer to do this?

7. Customer Facing Skills : Only few people have this skill and like to be infront of customers. You need to have some thick skin and take all the yelling :) ..Imagine when you are presenting or giving a demo to a customer and your tool crashes everytime you invoke it :) , scary is’nt it? okk..lets ease up a bit, it crashes only few times, how can you face the customer now? You should be able to ease and control the situtation …I can list hundreds of scenarios like this . It also takes a great deal of energy to say NO to a customer. Believe me its not an easy situtation. You need to be diplomatic when saying so sothat relationships are’nt hurt . It all comes by experience and ability to dynamically change the situtation on the fly :)

8. Issue Management : Very important skill . Should be in constant touch with the customer , track down the issues and have a proper resolution to all their issues with a fix schedule . It is important that the customer acknowledges and is actually OK with the fix schedule.If the schedule is missed for any issue, customer should be informed immediately.

9. Time management : Ability to multi-task is a must.

10. Debugging Skills: If you are not good in debugging or cant debug fast enough, you dont fit to be an Appln engineer.

11. Attitude : Having a proper attitude and ability to learn things fast is necessary to suceed in the job. You might need to learn different technologies, products/tools to perform your job better.
12. Peer-Peer Commn : Try to maintain peer-peer communication. There is no book which teaches on how to debug faster or perform each of the above skills I mentioned sofar. It is only through peer-peer communication you can learn . You might have an experienced AE in your organization, who can give you pointers ; its not that you cant solve it , Its that the other AE has done it 100 times and so knows the common pitfalls . You can avoid doing the same mistakes and save your valuable time.

13. Product Strategy : This requires knowledge in competitors products and its features , different technologies , business sense. Only then you will be able to place the product strategically infront of the customer.

14. Licensing Model : It is not essential , but very good skill to posses and understand how the licensing works like what features can be licensed ( to understand this, you need to justify why the customer will pay for this in the first place ) . If you know of any other venues through which you can generate a revenue for your software, it surely helps the Sales organization. Remember sales fix everything :)

In short, appln engineer is best evangelist an EDA company can have. He is the face of the company , best knowledgeable (technical) person who can deliver solutions out of the box, best person who has access to people who use the tool and therefore can promote the product to real decision influentiers , best person to give feedback to the marketing and sales organization, drive the product usability in the field, enhance and validate the product ( and its features) ;

So sounds like fun job right!! Atleast I love it and I’m being constantly challenged with newer technologies , products, sales and marketing campaigns:)

I would appreciate any feedback or comments.

-Kiran Bulusu, Semiconductors Expert, Technologist