This will gain momentum once design industry starts seeing “the value of ESL” .
Still a very niche area and we gotta see how calypto does and breaks the barrier…but I gotta tell ya…I’m impressed with their technology..
I have recently seen many folks asking questions like “How to write a synthesis script” or “Whats is in a synthesis environment” . Many freshers right out of the school claim to know about synthesis but in reality doesnt have a clue where to start.
When I refer to Synthesis in this post…I mean Logic Synthesis and I mostly cover only logic synthesis and it doesnt include any STA (Timing analysis). I will cover some points which overlap between logic synthesis and front end timing optimization. I will write a seperate post on Front-end timing optimization and Physical Synthesis (Floorplan , Global Placement and Routing , CTS ).
Synthesis is not just a script you write for a specific tool. It is actually much more than that. I have seen many folks who loosly couple it with a specific tool like Synopsys DC or Magma Blast Create. It is in a sense a methodology which evolves over the time by doing many runs as the block/chip evolves. Before you start synthesis , One has to know
1. What are the area goals? If area is one of the important criteria, then one needs to know what are the area reduction techniques available from the tool . I’m assuming that RTL has conforms to best design practices. Check the number of logic levels and cells used after first iteration. Accordingly decide what your strategy for area reduction should be. One benefit of reducing the area will help to comeup with a relatively smaller floorplan. Ofcourse most EDA folks prefer bigger floorplans sothat their floorplanning or placement tools can easily do the job , easily avoid the congestion and cross-talk issues :). But I strongly suggest synthesis folks to have some understanding of physical synthesis.
2. What are the power goals? Some tools have advanced power savings schemes in synthesis itself like Power gating flops/Retention flops. They do this when the RTL designer uses some special pragmas in their RTL code and they capture this when the tools parse the RTL.
3. If clock gating allowed? Are there any modules/blocks for which clock gating has to be disabled? You need to understand why it has to enabled/disabled and should be aware of its impact. You should know if the technology library has the support for ICG (Integrated
clock gating cells) .
4.How much hierarchy has to be kept? Keep in mind that Logical Hierarchy is different from Physical Hierarchy. When you decide to maintan hierarchy, it has to be considered that some optimization algorithms are limited by the module hierarchies/boundaries and so care should be taken as if and how much QOR can be sacrificed.
5. Is flattening allowed ? The answer to this question depends partly on the decision you make on the above question. If yes , is it allowed on entire design ? If not, can you atleast do flattening selectively. Other relevant information you need to know is , if rtl inferred models can be flattened .
6. What is your DFT strategy and methodology. Many might wonder why is it important to consider at Logic Synthesis stage. This is especially important when you plan for DFT during RTL development. Like you might have declared the test/scan ports in RTL and since scan insertion will not be done till synthesis has been done, many optimization algos in the synthesis engine will see them as floating and will blow them away. So, you might need to instruct the tool not to touch them.
7. Resource sharing and Operator Merging : If the these options are available in the synthesis and if you dont have any constraint or reason for not using them, then it is highly recommended to take advantage of these . But care has to be taken as some formal tools either dont have good support for this or dont support them at all .
8. Datapath architecture selection : Some advanced synthesis tool allows you to configure/pre-select the datapath architectures . If timing is critical for a particular block, then you might want to overide the area optimization steps by selecting the fastest architecture available for all the datapath components in that particular block. Do remeber that selecting fastest architecture might blow up area sometimes.
9. Formal Verification : FV (Formal Verification) tools dont do agressive optimizations ( or should I say, it is not a good idea to so ) as synthesis tools do. So, it is highly important that you let your FV tool know about the synthesis options when exists & possible. You should try to mimic the synthesis env in your FV environment. Else you can see some false failures.
10. Hard Macros : When macros are used and if some of the inputs/outputs are unused, they might be removed. So if any macros or hard instantiated gates are present , you should set the appropriate commandslike force keep or set_dont_touch .
11. Spare gates/registers : When spare registers are described in the RTL itself, synthesis tools should be instructed to preserve them else they are treated as a part of unreachable registers and might be thrown off during
synthesis (deadcode removal ). Some people use spare registers in the backend and sprinkle them evenly.
12. It is important to analyze the technology library for the cell delays and area. One another important factor most people forget is to consider the effect of EM (electro-migration) and yield . All the bad cells ( which have high delays , or bad for EM or yield, bad area ) should be hidden or disabled from being used by synthesis engine. Forgetting to disable cells bad for EM or yield effects timing closure with cross-talk/SI during backend.
Apart from this, make sure all complex cells like AOI, OAI, Full Adders and Half Adders, XOR etc are available to the synthesis tool. It helps save area and increases drive load capability resulting less buffering.
13. Dont use highest effort levels in synthesis by default ( unless you know what you are doing ). Some optimization algorithms might hurt your design by doing agressive optimizations. Synthesis knobs have to be used with care and by studying what it does to the design.
14. Designware usage: Sometimes, it makes sense to use Designware components in RTL . Make sure the synthesis tool used can detect the Designware components , understand and synthesize them. Some synthesis tool vendors change them to their equivalent models ( for example, Lavaware components from magma ) . If not , you might need to black box them and read in the gate level netlist of those designware components after synthesis is done.
15. Pipe-lining : Almost all synthesis tool support this . So where necessary, the designer or synthesis expert has to know which block/module needs pipe-lining ; how many stages are required and what is the latency at each stage etc.
16. Re-Timing : Sometimes when RTL has those designware or lavaware components , some synthesis tools automatically apply re-timing and some synthesis tools require you to explicilty set the relevant re-timing configs . But keep in mind that re-timing is not supported that well in FV tools.
17. Dontcare optimization : If the RTL contains dont-cares (X) , many synthesis tools allow you to choose whether you want x to be treated as “0″ or “1″. I suggest it would be better if we leave it to the synthesis tool to decide. Most dontcare algorithms select the value of x which will result in smaller ckt area if area optimization is enabled or better ckt with better timing if timing mode is enabled.
18. Clock Edge mapping: Some synthesis tool map to neg edge flops and add a inverter if they see that is has better area savings than pickingup a pos edge flop. Some design methodologies especically back-end teams dont prefer this sometimes. So, you need to set the configs accordingly.
19. If there are any complex cells like Full Adders, Half Adders etc with multiple outputs in your library , then most synthesis tools dont utilize them and so if your want to synthesis tool to use them , then you have to hand instantiate them in RTL. Remeber these cells will be timed, but will not infered or decomped to simpler cells/logic during optimization phases .
With all these said, I cant stress enough how important it is for RTL coders to follow best practices. There is lot of information out there or one can refer to STARC methodology guide or Design-Reuse methodology manual for information .
I was just thinking why cant the Marketing folks in EDA companies have a agreement with the Semiconductor companies that when a chip goes to production , their logo is displayed as well. Something like Designed using Magma Design Automation etc., I cant think of reason why Semiconductor companies wont allow that. I think it will create much more buzz than a press release. It will also expose the EDA industry and the company to outside world . The role played by the EDA industry right from RTL-GDSII and post silicon debug is very important and cant be downplayed .
For example, when we look at the IPOD and scrolldown to a section (something like about us ), you can typically see that the chip is designed by Portal Player etc. So, if Apple allows Portal Players logo to be on IPOD, why cant they allow EDA company name to be there. Yes, I understand that it is not as simple as it sounds as many chips deisgned by one company gets integrated into another company’s SOC , but still, it can be done through
It helps EDA companies to get the recognition they deserve and also it helps EDA companies to attain a brand similar to what product based companies have.
It is a long post (you are warned !!
I have been recently asked by someone as what it takes to be sucessful application engineer . So, I thought why not blog about ..Though much of it is written from EDA industry perspective, it applies for appln engineers in other industries as well. So, here it goes ….
1. Technical expertise : You have to be atleast good if not proficient in the domain..for example, lets say, if you are application engineer for a formal verification product, you need to have expertise in the FV techniques and good understanding as what logic/physical synthesis tools do in terms of optimization. Just mere tool knowledge will not suffice..
2. You should be a like a double edged sword ..You need to be able to understand the hardware design…be it RTL , Scan insertion , P&R or CTS and at the same time , you should be able to understand how the algorithm (tool) behaves (from software perspective..)..If you dont understand both, you will not be able to understand what the HW designer is trying to accomplish and at the same time, you will not be able to find out if the tool is missing any feature or is it a limitation of the technology and finally if it is a bug …one more important reason is , you might need to translate the designers intention into a feature speficiation and direct your R&D.
3. Business Sense : I think this is very important component for an Appln engineer. You need to be in constant touch with the customer and get feedback on the product. You should be able to sense the impact derived from that feedback. Whenever there is a oppurtunity to promote a new product, you should do so immediately and let your marketing/sales team know about it immediately. Just being technical is not enough.
Application engineer without good business sense can negatively impact the company he represents.
4. Pre-Sales : Ability to benchmark against the competitor and convince him about your products technical merits. Depending upon the competetion and product and domain in which you operate, this can be very intensive and grilling. Failure is not an option . A true winning aptitude and to do whatever it takes is absolute must. No compromises.
I’m not exagaretting , but it might involve some sacrifices like working during xmas or thanksgiving . Pre-Sales campaigns can very stressful and can burn a person. So, if you cant work under pressurized environment and have strict rules about your work timings, then you might not like this role. Believe me there are some customers who keep evaluating for very long time or they evaluate now and then re-evaluate after couple of months and there are reasons why they do like this ( first and foremost reason is to check the quality of the tool ) . So it is tiresome and it requires willingness to walk that extra mile to win the benchmark is a must.
5. Post-Sales/Deployment : A succesful tech campaign and business(pre-saleS) win is the starting step. The 20/80 rule applies here ( 80% of the business comes from 20% of your customers). So, sucessful deployment of the product across the depth and breadth of the company is key . It will also gives Sales folks a chance to push other products
into the company. Dedicated and fast support is one of the strategies. Providing support for their first tapeout with your company’s product is another key. A sucessfull deployment also means to work with the design methodology groups,designers ( front end and backend ), understanding their design goals and issues ; resolving their issues . It might be necessary to come up a design methodlogy /flow either on a project basis or company wide . A constant interaction with the design team is a must . This also helps the appln engineer to see what is lacking and fill in the gaps either through scripting or getting R&D implement the missing features and enhance the product.
6. Evangelism : Not many folks know about this. Some people mix this with the marketing. This is virually non-existent in EDA/semiconductor industry. Marketing is more about the product , evangelism is creating a community around the product. Who else can be a better person other than the appln engineer to do this?
7. Customer Facing Skills : Only few people have this skill and like to be infront of customers. You need to have some thick skin and take all the yelling ..Imagine when you are presenting or giving a demo to a customer and your tool crashes everytime you invoke it , scary is’nt it? okk..lets ease up a bit, it crashes only few times, how can you face the customer now? You should be able to ease and control the situtation …I can list hundreds of scenarios like this . It also takes a great deal of energy to say NO to a customer. Believe me its not an easy situtation. You need to be diplomatic when saying so sothat relationships are’nt hurt . It all comes by experience and ability to dynamically change the situtation on the fly
8. Issue Management : Very important skill . Should be in constant touch with the customer , track down the issues and have a proper resolution to all their issues with a fix schedule . It is important that the customer acknowledges and is actually OK with the fix schedule.If the schedule is missed for any issue, customer should be informed immediately.
9. Time management : Ability to multi-task is a must.
10. Debugging Skills: If you are not good in debugging or cant debug fast enough, you dont fit to be an Appln engineer.
11. Attitude : Having a proper attitude and ability to learn things fast is necessary to suceed in the job. You might need to learn different technologies, products/tools to perform your job better.
12. Peer-Peer Commn : Try to maintain peer-peer communication. There is no book which teaches on how to debug faster or perform each of the above skills I mentioned sofar. It is only through peer-peer communication you can learn . You might have an experienced AE in your organization, who can give you pointers ; its not that you cant solve it , Its that the other AE has done it 100 times and so knows the common pitfalls . You can avoid doing the same mistakes and save your valuable time.
13. Product Strategy : This requires knowledge in competitors products and its features , different technologies , business sense. Only then you will be able to place the product strategically infront of the customer.
14. Licensing Model : It is not essential , but very good skill to posses and understand how the licensing works like what features can be licensed ( to understand this, you need to justify why the customer will pay for this in the first place ) . If you know of any other venues through which you can generate a revenue for your software, it surely helps the Sales organization. Remember sales fix everything
In short, appln engineer is best evangelist an EDA company can have. He is the face of the company , best knowledgeable (technical) person who can deliver solutions out of the box, best person who has access to people who use the tool and therefore can promote the product to real decision influentiers , best person to give feedback to the marketing and sales organization, drive the product usability in the field, enhance and validate the product ( and its features) ;
So sounds like fun job right!! Atleast I love it and I’m being constantly challenged with newer technologies , products, sales and marketing campaigns:)
I would appreciate any feedback or comments.
I have been hearing about the design/IP reuse from time to time. Today there was an article on EE times which can read by clicking this link Design-Reuse
I think many big companies have adopted the reuse methodology and realize the benefits of it. Even small-medium companies re-use the blocks or IP’s in most of their chips. So, I dont think there is any need to keep repeating the importance over and over again. Most of the companies cut down their design cycle time and costs using this reuse methodology. I think now one should look forward and see if they can get good prototyping flow . I recently worked on prototyping efforts and it correlated very well with 90nm , 130nm and 180nm. For 65nm and below, special considerations have to be adopted like taking the account of parasitic effects . With this flow, the time to achieve timing closure is significantly smaller as designer gets early feedback.
I would appreciate if anyone has any experience in developing/using the prototyping flow and can share their concerns. It will be very informative and good discussion.
I often see some startup companies especially EDA companies ,which have big aspirations of going for IPO sometime down the lane ( ofcourse every CEO with help from CFO talks about taking the company to IPO)….but if we analyze how some companies are run in terms of their strategies, it wouldnt take much time to realize that their goals are not aligned with their vision….these startup companies forge a relationship with biggies in their field as partners/alliance . They dont (dont want to ) compete with the big companies in terms of their product offerings..they offer complimentary products which go along with the main stream products…essentially they are nice to have and not must have…so how can these companies grow and build a good revenue stream??
For example, take four companies companies , startup company A, a relatively young company B which is still pre-IPO , some tier II company C ( normally categorized based on revenue) and a tier I companies D and E . Company A has many products which all might be integrated and sold as suite of tools or maybe point tools which can be sold seperately depending on how the sales folks want to … all/most of the products they offer work along with the products of C,D and E. The current situtation in the EDA market is, company A is building relationships with B,C,D and E and is positioning itself strategically sothat it has no competitors and it doesnt get biten by the aggressive Tier I or Tier II companies….But what company A is not realizing is..this way of forging relationships doesnt help the company in long run as they wont have much space to grow and they cant increase their revenue stream by just refining their existing products or adding nice to have features…Company shouldnt get lost or spend all of its energy on how to survive…it should rather formulate a strategy which helps the company to survive and generate revenue ( by having a cashcow product) and then it should be able to quickly have products which can differentiate itself from the rest and compete either alone or with the help of alliance it has formed earlier…
In our example earlier, If companies C,D and E cancel their partnerships and they start to offer the features which company A has planned, it doesnt take much time for the company A to look for potential buyers… Companies can forge relationships and alliances, but when creating strategies, it has to do it in such a way that it has space to grow and the alliance helps it in creating even more powerful products and has created uncontested market space…. To create that you need :
1. World class R&D team : From my experience, I see that customers prefer products which which cuts costs ,time or both if you are in EDA…There are many EDA companies whose value proposition lies in simple economic fundaes like reducing time and money spent on other main implementation based tools…there are about 10-12 startup companies operating in EDA space
with this value proposition..
2.Marketing ppl who can brandize the product, a good example is that of XeroX…When they entered India, they marketed it so much..ppl often refer Photocopying as Xerox..you can see Xerox machines everywhere ( not photocopying machines!!) …whatever you do, the customer
should be able to feel it…it should revolutionalize the way your customers think about it…Apple IPOD is one decent example,
3. Sales folks who can sell ice to eskimos and
4. Appln engineers : who can help customers and make them realize the product value ..thereby bringing more business/revenue to the company..remeber the 80/20 rule…80% of the revenue comes from 20% of the customers…so make these exisiting customers happy and bring in more customers by delivering the product value…
and Ofcourse, you need to have good CEO who has vision thats executable and backed by good executives who can strategize the business and take it down the straight path …path which leads to IPO…..
The De-Coupling point principle put forth by Clayton M. Christensen, Christopher S. Musso and Scott D. in their article “MAXIMIZING THE RETURNS FROM RESEARCH”, says that “The company developing a new technology must plan to integrate forward from the point at which a new technology is developed, across every interdependent interface in the chain of value-adding activities out to that point at which there is a modular interface with the next stage of value-added.” They say that, it is the activity just before the decoupling point where the most attractive profitability in the value chain can be achieved. The reason for this is that performance in a modular product is not determined within the product’s architecture, but within the subsystems from which the modular product is assembled. At the stage of value-added just before the decoupling point, performance differences are determined primarily by the interdependent architecture and less by the components that are used.
EDA industry is very competitive and is more technology driven than any other field in the IT industry. As the design complexities increase, designers demand more innovative and complex tools and as the time to market pressures are increasing (for many chips it is less than 6-9 months), EDA companies are always under great pressure to roll out sophisticated tools to understand and solve design complexities . Having said this, it can be easily understood that EDA industry works in tight integration with the Design companies and the manufacturers. Each chip is designed in a different way and the Methodology engineers propose new
Methodologies and flows which indirectly puts pressure on the EDA industry.
Now let’s look at various perspectives: An EDA Startup Company can roll out sophisticated software for a specific stage in the ASIC/FPGA/Structured ASIC design flow. The problems typical EDA start-up companies’ faces are: They have to make sure that the algorithm on which they built the software delivers both the performance (how fast the tool can analyze the design sources say RTL or Netlist) and the design capacity it can handle (20 million gate design is very typical now-a-days), the output of the tool should be compatible with the tools from the four big giants (Cadence, Synopsys, Mentor and Magma) so that the designer can take the output from the tool and use it in the next steps of the design flow with the implementation tools. The tool interoperability issues are always a painful task for the EDA engineers.The success rate for the EDA startups is very less for the reason said earlier. They have to see a way where their tool suite can be seamlessly integrated. So for EDA startups, the De-Coupling point lies in effectively addressing the design complexities, able to handle higher capacity and performance that the competitor tools. But the companies have to keep in mind that de-coupling point might shift to higher point in the value chain.
For an already big company like Cadence, Synopsys and Mentor, their de-coupling point doesn’t lie in the new tool offerings, but rather understanding the design flow gaps in the already offered tools and quickly filling it out and thus enabling a better and fully integrated platform.
If anyone out there has any ideas/opinions on the de-coupling point…please comment….